minimal counter configuration experiment ::
?! it's even possible . . . in theory . . .
+MMXV-02-08 the pulse T-trigger speed test
- thought to run this test in real but . . . what's the point -- it'd take also to build/test/verify a 15M detection circuit - that'd be more complex than the one below . . .
notice the complexity differences in between above and below circuits -- the speed difference seems to be roughly 1:3 . . . such as does it weigh up to gain some more speed by this "investment" , becides pushing the chip to it's limits increases the likelihood for errors
+MMXV-02-08 the pulse T-trigger speed test
- thought to run this test in real but . . . what's the point -- it'd take also to build/test/verify a 15M detection circuit - that'd be more complex than the one below . . .
notice the complexity differences in between above and below circuits -- the speed difference seems to be roughly 1:3 . . . such as does it weigh up to gain some more speed by this "investment" , becides pushing the chip to it's limits increases the likelihood for errors
! Update 2021.08.01 :
found an error in the above circuit , a repair as a (at the input the XOR must be faster than the NAND-s or the NAND-s should be delayed to be slower for proper operation)
found an error in the above circuit , a repair as a (at the input the XOR must be faster than the NAND-s or the NAND-s should be delayed to be slower for proper operation)
[Eop]
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