Sunday, October 26, 2014

Switched inductorless DC→DC converter TEST

the TEST trg./ (fig.1) got my interest by it's switching capacitor name values (1µF) v. V.OUT parameters -- I.max = 50mA U.TOT = 30V . . .

. . . the simulation showed that the transistors at the same "shoulder" are OPEN @ the same (short) time + the generator wave forms were somewhat not that you'd expect

(i guess presented in the ® order ) the figures show the improvement/TEST steps - to meet proposed OUTPUT parameters to this 9V : 30V converter

note : the peak currents approach 1A range - the averages - are the way over the specs of the 1-s of the initally shown* transistors (in test the 2N3906*,-04* was used to get the oscillations started) /!\ -- you likely can't build any of the shown grids ( using these* transistors ) that would survive the switch ON + further more (i suppose) using the 6LF22 / 6LR61 or alternate won't meet the power demand of "this" converter the 6x AA / LR6 or better is more realistic

Figures ::
  • Fig.1 :: the ® - a lot of question marks
  • Fig.2 :: 68% OUTAVG 28V 51mA INAVG 8.4V 250mA
  • Fig.3 :: 64% OUTAVG 25V 44mA INAVG 8.5V 200mA
  • Fig.4 :: 74% OUTAVG 29V 51mA INAVG 8.4V 230mA
  • Fig.5 :: 79% OUTAVG 35V 63mA INAVG 8.3V 340mA
  • Fig.6 :: 74% OUTAVG 38V 43mA INAVG 8.4V 260mA








Thursday, October 9, 2014

... Let's put some sh­¡t up e.g. the weird science about MEM and SCS/SCR

What's good about the Blogger if you dont blog , ? yes.

(re-)starting with a lot of diodes 1N4148 + 2N3906 , 2N3904
trying 2-def a microbe-hour csc flip-flop
... it's below the lower half of the kHz range
to induce re triggering - takes deviating from std.
about 170 Hz operation (amazingly valid for full possible supply range ???)

teh prev. "defined" crash-ware (oldies)
Bench for a single stage
~ about 30kHz op.-s
. . . . . . . . . i finally get this memory cell working . . . . . . . . . 20kHz write (with ultra cool power draw)
. . . WHAT WAS UPLOADED WAS 2048x1512px133KB(136733bytes)
??? -- SORRY I GOT IT WRONG AGAIN SO GOOGLE HAD TO "FIX" IT - g.d. perverts - they just can't leave anything untouched . . .
. . . ok, (it's just) yet another totally unnecessary "optimization" by Google ________ come on it's just a few lines to add to your server code (run 1-ce(onece) per img. upload) to tell whether you managed to increase

1-st - the i-net bit traffic on each(every) future page request
2-nd - thus everyone elses' wait time (making i-net slowwer)

 . . .ok that's about how fast we runn off the fossil fuels , but

 ? what i suppose to do ? chk each time if my img.-s're ok ?? and if not
 ? split'em into smaller frames ,
 ? write extra code for each frame
 ? (uploading 4 images (3 extra file headers) instead of 1)
???? delete the "not successful" upload from "blogger album" (takes to wait all blog images to load b4 you can delete any particular 1 OR navigate from 1-st to requred to delete 1) - in "one word" make a day full of job out of what should've taken 2 minutes

why i always have to take a day free to uplaod single image - IT JUST SO ABSURD AS IT IS

 . . . sorry i don't need to purpose my salary to figure out another "virtual task" - i don't get your game to be honest (perhaps you're just stupid or smth. out of my reach)

this is not a ready to use stuff
a snapshots from on going research dev.
it's like @ this Z-up  the grid does THAT

Monday, October 6, 2014

Flip-Flops' Speed TEST

those things are most always required fast , so . . .

. . . 3 , 2 , 1 , exit *

Excel v. LTSpice

since the decoder's quite complex (and unoptimized) then , to avoid unnecessary head ace , i QC-d it's operation on "spreadsheet model" , the head ace however started with defining the OC functionality in Switcher CAD - which i donno about if it's fully ok the way it finally got implemented ...

/!\ -- pay attention to the R3 to R3 ratio in macro model ↓↓ and in test ↑↑ circuit (before you use this feature in your own simulation) -- /!\

... a digital head ace ::


Wednesday, October 1, 2014