about Discrete Logic Simulation Specifics

(about: LT Spice analog signal simulation) sometimes adding a dummy LC resonator (AND/OR adjusting the "minimum timestep") improves the fine detail in simulation while sometimes it takes to kill all possible Hi-Fq. src. paths with large enough inductors to avoid "Timestep too small" errors ...

(+ some Discrete Logic Simulation Specifics) there seems to be a strong "INTEGER SYNCHRONICITY" - a programmatic synchronicity - in between the Digital grid and it's driving signals -- such as the fine adjustment of pulse timing parameters can give you drastically different simulation results -- it may occur also important to "RESET/initialize"(electronically) your circuit in very specific way for it to start and keep operating "/!\normally/!\" ◄◄ such is trivia in complex digital designs but here it gets extended with the INT SYNC. + unknown by me the LT-Spice specifics

some (random) Digital TEST-s

(the last is not 100% verified attempt of idiot-proofing the D-trigger)